NurLogic Delivers Quad 3.318 Gbps SerDes Transceiver Cores Offering The Industry's Most Comprehensive Feature Set
NurLogic Generates 0.13-Micron SerDes Cores With Extensive Design Flexibility For Use In Systems Built Around 10-Gigabit Ethernet (XAUI), Infiniband, Gigabit Ethernet, Fiber Channel Architectures
SAN DIEGO, CA--(INTERNET WIRE)--Apr 8, 2002 -- NurLogic Design, Inc a developer of high bandwidth connectivity
solutions, today announced the immediate availability of
its portfolio of SapphireLink(TM) serializer/deserializer
(SerDes) transceiver cores. NurLogic's 0.13-micron SapphireLink
SerDes cores support data rates of 1.0 Gbps to 3.318 Gbps
per channel, delivering flexibility as well as capability
to developers of networking communications chips. NurLogic's
products are particularly attractive to developers due to
programmability and customization capabilities to meet the
needs of a wide range of applications, speeds and design
requirements.
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NurLogic Design, Inc. | |
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NurLogic SerDes Core |
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NurLogic's SapphireLink SerDes IP cores provide high-bandwidth
connections between router backplane links while supporting
an 8B/10B encoding/decoding scheme with clock recovery for
embedded clock applications. The SerDes IP cores' well-defined
architecture provides a comprehensive feature set that allows
SoC designers extensive flexibility for a wide range of
system interface options and system level applications including
10-Gigabit Ethernet (XAUI Interface), Infiniband, Gigabit
Ethernet, and Fiber Channel. NurLogic's implementation of
this product as a "hard" IP core allows for higher system-level
integration, which is more cost competitive than discrete
SerDes IC products."Customers are looking for high-speed interface solutions
from a supplier that has strong expertise in mixed-signal
design and integration, as well as a proven track record
of designing high speed I/Os, PLLs, and CDRs. NurLogic firmly
believes our SerDes cores will meet customer performance
needs in all areas," said Lisa Lipscomb, vice president
of marketing for NurLogic. "Our technology has always played
a significant role in meeting market demand for performance,
low power, bandwidth, and time-to-market requirements of
our SoC customers. We expect our SerDes to be well received
in the industry because it places cost management, performance,
and scalability in the hands of system developers."
NurLogic's SerDes cores provide higher performance, lower
power consumption, and smaller physical sizes that allow
SoC designers extensive flexibility and scalability for
a wide range of applications. The SerDes cores exhibit key
capabilities to help designers maximize productivity as
well as product quality. NurLogic's Quad SerDes cores accept
an 8/10-bit or 4/5-bit core interface with Single Data Rate
(SDR) or Double Data Rate (DDR) options. This design incorporates
many testability features including: Built-In Self-Test
(BIST), serial and parallel loopback, IDDQ, boundry scan,
and Pseudo Random Bit Steam (PRBS).
PRODUCT HIGHLIGHTS
NurLogic's SapphireLink SerDes cores are implemented as
4-channel (Quad) physical representations that allow for
ease of integration. This modular design allows for multiple
instantiations without performance degradation and meets
the speed requirements for OC768 applications. The NurLogic
SerDes cores can be used in networking applications and
can perform parallel-to-serial, serial-to-parallel conversions
for physical and link-layer devices up to 3.318 Gbps.
FEATURES:
* 3.318 Gbps per channel, 13.272 Gbps for quad core
* Low Power Dissipation -- 80mW per TX/RX pair
* 8B/10B Encode/Decode with bypass option and comma detect
* Clock and Data Recovery (CDR) on each RX channel
* AC/DC coupled CML with programmable
pre-emphasis/amplitude adjust
* Half power CML for power savings
* On-chip programmable terminations of 50 ohms +/- 10%
* Loss of Signal (LOS) detect, up to 90 bits
* Multiple pattern options including K28.5/K28.7/D16.2
* Hot swap capable I/Os
* Testability features: Serial and Parallel loopback,
IDDQ, Boundry Scan, Built-In-Self-Test (BIST), Pseudo
Random Bit Sequence (PRBS)
FLEXIBILITY:
* Modular design for ease of integration
* Superior noise isolation allows integration up to 64 channels
* Parallel Interface options for LVDS, HSTL, SSTL2 (XGMII)
* Flexible parallel interface - 8/10-bit parallel up to 312 Mbps
or 4/5-bit up to 622 Mbps
* Option for eye centered reference clock
* Support for SXI5 I/Os
* Wirebond or flip-chip options
* Double or single data rate optionAVAILABILITY
NurLogic offers the SapphireLink SerDes core portfolio as
"hard" IP blocks that include support for leading EDA tools
and foundry technologies. NurLogic's 0.13-micron SerDes
cores are currently available to license. Pricing is available
upon request.
About NurLogic Design, Inc.
NurLogic Design, Inc. provides high-bandwidth connectivity
solutions to the networking and communications industries.
NurLogic's products encompass customer-specific and industry-standard
integrated circuits and semiconductor intellectual property
to deliver value-add to its customers. NurLogic products
are targeted at CMOS and silicon germanium technologies,
and include high-speed connectivity IP, analog and mixed-signal
IP, foundation IP, and PMD and PHY ICs. NurLogic is the
recipient of the 2001 Most Innovative New Product (MIP)
Award in a competition sponsored by the University of California-San
Diego (UCSD) CONNECT program for its 48-channel optical
interface chipset design. Based in San Diego, California,
the company has regional sales offices in Massachusetts
and Silicon Valley. NurLogic is a privately held corporation.
Headquarters: 5580 Morehouse Drive, San Diego, Calif. 92121.
Tel: 1-877-NURLOGIC. On the web at www.nurlogic.com.
NurLogic is a trademark of NurLogic Design, Inc. All other
trademarks are the property of their respective owners.
Copyright 2002 NurLogic Design, Inc. All rights reserved.
